The present invention relates to timing alignment for demodulation of a digital signal and, more particularly, to signal timing alignment using a delay lock loop (DLL) in Direct Sequence Spread Spectrum (DSSS) communications.
Spread spectrum communication schemes were originally developed for the military to solve the problem of signal jamming by an enemy. The basic idea behind spread spectrum is that by broadcasting a signal over a wide range of frequencies, the enemy is prevented from jamming the signal. There are three main types of spread spectrum communications: Frequency-Hopping; Direct Sequence; and Hybrid. The Frequency-Hopping scheme avoids jamming by hopping from frequency to frequency in a pattern known to the transmitter and receiver but not to the jammer. In Direct Sequence Spread Spectrum (DSSS) communications, a transmitted signal is broadcast over a very wide band of frequencies to avoid narrow-band interference. Because a transmitted signal is spread over a broad frequency band, many transmitters may be broadcasting in the same bands. DSSS systems use a unique identifier code assigned to each transmitter to enable a receiver to separate a signal of a particular transmitter from that of all the other signals in the same bandwidth. Hybrid spread spectrum schemes are a combination of the Direct Sequence and Frequency-Hopping schemes.
One example of a DSSS-type system is a Code Division Multiple Access (CDMA) type system. In a CDMA type system, multiple users simultaneously communicate while sharing the same wideband frequency spectrum. Each of the users is assigned a unique digital pseudonoise (PN) code sequence. During transmission, the PN code sequence is used to spread the transmitted signal over the CDMA frequency spectrum. Spreading is sometimes referred to as xe2x80x9cchippingxe2x80x9d because each bit of the signal is chipped into xe2x80x9cchipsxe2x80x9d by the spreading code. In other words, a bit to be transmitted is broken down into chips by the spreading code and, after transmission, the chips are reassembled into the original bit at the receiver. The spread (or xe2x80x9cchippedxe2x80x9d) signal is then RF modulated and transmitted on a carrier frequency. The same carrier frequency may also carry other users"" transmissions that have been spread by their unique PN sequences. Transmissions by all other transmitters appear only as additional noise to a receiver listening to a particular transmitter. Assuming that all the transmissions are received at approximately the same power level, carefully choosing the PN code sequences to be orthogonal allows the noise from the other transmitters to be filtered out by the receiver.
Synchronization of PN code sequences between the receiver and transmitter is a serious problem in DSSS systems. To accurately decode a DSSS transmission, a receiver must synchronize its PN code generator to the transmitter PN code generator. Synchronization is usually accomplished in two steps. The first step, called acquisition or detection, includes bringing the PN code sequences generated in the transmitter and receiver into coarse alignment, typically within one code chip interval (in other words, within one chip period). The second step, called the time tracking loop, involves fine synchronization to the received signal and continuous tracking to maintain the best possible waveform alignment during reception by means of a feedback loop. The time tracking loop corrects for the Doppler effect as a mobile station moves toward or away from a base station.
Due to the importance of synchronization in DSSS systems, many synchronization schemes have been proposed that utilize various types of detectors and decision strategies. A common feature of most synchronization schemes (such as the maximum likelihood acquisition method discussed below) is that the received signal and the locally generated PN code sequence(s) are first correlated to determine the measure of similarity between the sequences. Next, the measure of similarity is compared to a predetermined threshold to decide if the signals are in synchronization. If there is no synchronization, the acquisition procedure provides a change in the phase of the locally generated PN code sequence and another correlation is attempted as a part of the signal search through the receiver""s phase space.
Initial acquisition or detection of a DSSS signal may be accomplished using the maximum likelihood acquisition method. In maximum likelihood acquisition, the received signal and the locally generated PN code sequence(s) are first correlated in the receiver to determine the measure of similarity between the signals. Next, the measure of similarity indicated by the correlated results is compared to a threshold to decide if the two signals are in coarse synchronization. The threshold may be determined a priori or may be an adaptive threshold, set according to the results of correlations with previous PN code phases. In the adaptive threshold method, the entire PN code space is searched and the PN code phase resulting in the maximum threshold is used to receive further communications.
Most American CDMA cellular (mobile) systems operate according to the Telecommunications Industry Association/Electronic Industry Association (TIA/EIA) IS-95 cellular system standard. IS-95 is also commonly known as CDMAone.
In an IS-95 system, the downlink transmission consists of at least one common channel and a number of radio channels. A permanent signal is transmitted on a common pilot channel. It may be used by the mobile for coherent communication to estimate the path loss, so as to set power control initially, and to acquire synchronization to the network. Additional channels are set aside for paging and other downlink information.
In an IS-95 system, a mobile station must quickly search, acquire, and synchronize to many different signals while maintaining communications with the system. The mobile station must initially acquire a pilot channel from a base station of the system upon power-up or entry into the system. As the mobile station moves through the system, it must continually search for stronger pilot channels of base stations located near the base station with which the mobile station is communicating. The mobile station searches for pilot channels based on PN pilot channel phase information received from the system. The pilot channels in IS-95 are transmitted by each base station using the same system PN code but with different phase offsets. The code phase offsets allow the pilots to be distinguished from one another and thus uniquely identify each base station to the mobile station. All pilot channels in the IS-95 system use Walsh code 0 (a sequence of all 1""s).
In an IS-95 system, when the mobile station has detected acquisition of a pilot channel of a certain base station (or system) PN code phase, the mobile station attempts to decode a synchronization (SYNC) channel at the same PN code phase. This SYNC channel is spread by the base station PN code phase and a unique Walsh PN code sequence that identifies the SYNC channel transmissions. The SYNC channel frames transmitted on each SYNC channel from each base station are aligned with the pilot PN sequence of that base station, so correct detection and acquisition of the pilot channel allows the SYNC channel frame to be received and decoded. The SYNC channel frame includes a SYNC Channel Message that provides system parameters to the mobile station. The system parameters in the SYNC channel frame include the timing of the base station""s pilot sequence with respect to the system timing and the base station""s paging channel data rate. Once the mobile station has obtained information from the SYNC Channel Message, the mobile station adjusts its timing to correspond to the system""s timing and begins monitoring the paging channel.
If the process of synchronizing to the system, which includes acquiring the pilot channel and synchronizing to the SYNC channel, involves false detections of the pilot channel, significant penalties in time may result. In IS-95, if a mobile station falsely detects a pilot channel the mobile station attempts to transition to and decode the SYNC channel. The mobile station may spend up to one second attempting to decode the SYNC channel, after which the process of acquisition and synchronization will start again. The time spent attempting to decode the SYNC channel after false detection of the pilot channel is significant, when taking into account that acquisition and synchronization times of less than two seconds are typical goals for mobile station manufacturers.
There are basically two mechanisms within a CDMA receiver to provide proper chip timing alignment (synchronization) for demodulation. The first is referred to as PN acquisition, where the coarse PN alignment of the received signal is found using a locally generated replica of the PN sequence. This alignment is usually within one chip period, the accuracy of which is a function of the sampling rate used for acquisition. The second mechanism is the time tracking loop, which in spread spectrum systems is commonly referred to as a delay lock loop (DLL). The task of the DLL is to attain and maintain fine timing resolution, thereby providing the optimum timing epoch for the received data in the receiver.
In most DSSS systems the time tracking loop error detector is designed using a noncoherent DLL. Various schemes exist to implement these timing error estimators (Tau Dithered, Early-Late, Early-On Time, etc.). Noncoherent approaches are used because either the phase of the signal is not available to the tracking loop or there is data information which is embedded within the receive signal and is not known a priori. FIG. 1 shows a typical (prior art) receiver with noncoherent Early-Late DLL structure.
Referring to FIG. 1, a signal y(txe2x88x92xcfx84) is received by an antenna 113 and passes through duplexer 114 to Analog-to-Digital (A/D) converter 101. The signal next passes to Sample Generator 102 which samples the digital signal. The signal y(txe2x88x92xcfx84) then is demodulated into information bits by Data Demodulator 103.
The time at which A/D Converter 101 and Sample Generator 102 operate on signal y(txe2x88x92xcfx84) is fine-tuned by the DLL. The DLL architecture shown in FIG. 1 is the Early-Late architecture, so named because the signal to the Late arm is delayed by xcex4 seconds and the signal to the Early arm is advanced by xcex4 seconds. An xe2x80x9carmxe2x80x9d of the DLL circuit is typically a portion of the circuit that is electrically parallel with another portion of the circuit but can be generally thought of as a path through a portion of an electrical circuit. Multiple xe2x80x9carmsxe2x80x9d are not required. For example, if a DLL only operated on either the Early signal or the Late signal, the Early (or Late) signal path through the DLL would be considered an xe2x80x9carmxe2x80x9d even though it is not electrically in parallel with a Late (or Early) signal path. The Early signal y(txe2x88x92xcfx84+xcex4) is despread with PN code sequence c(t) by Correlator 104. The Late signal y(txe2x88x92xcfx84xe2x88x92xcex4) is despread with PN code sequence c(t) by Correlator 105. Both correlated signals pass through their respective Filters 106, 107 and Magnitude Operators 108, 109. Only real components of the Early and Late signals remain after the Magnitude Operators 108, 109 have removed the phase components by performing a squaring operation. The real components are then subtracted from each other by Subtractor 110 to arrive at a difference which is known as the error signal e(xcfx84). In this example, the Early and Late signal arms begin at the node after Sample Generator 102 and end at Subtractor 110. The error signal e(xcfx84) passes through Filter 111 to Resample Logic 112, which adjusts the operation of A/D Converter 101 and Sample Generator 102 in response to e(xcfx84).
Some basic mathematical expressions describing the process in FIG. 1 follow. The equivalent lowpass input signal is expressed as:                               r          ⁢                      xe2x80x83                    ⁢                      (            t            )                          =                                                            2                ⁢                E                                      ⁢            c            ⁢                          xe2x80x83                        ⁢                          (                              t                -                τ                            )                        ⁢                          xe2x80x83                        ⁢                          ⅇ                              j                ⁢                                  xe2x80x83                                ⁢                θ                ⁢                                  xe2x80x83                                ⁢                                  (                  t                  )                                                              +                      n            ⁢                          xe2x80x83                        ⁢                          (              t              )                                                          (        1        )            
Where E is the chip energy, c(txe2x88x92xcfx84) is the received PN with the unknown transmission delay, xcfx84, n(t) is the complex additive noise, xcex8(t) is the unknown phase term consisting of a constant and a term proportional to the Doppler or untracked AFC phase term. The input signal is then sampled to give two delayed versions y(txe2x88x92xcfx84+xcex4) and y(txe2x88x92xcfx84xe2x88x92xcex4) that are correlated with the locally generated PN sequence to produce:             y      ±        ⁢          xe2x80x83        ⁢          (      t      )        =                              2          ⁢          E                    ⁢      c      ⁢              xe2x80x83            ⁢              (                  t          -          τ                )            ⁢              xe2x80x83            ⁢      c      ⁢              xe2x80x83            ⁢              (                  t          -                                    τ              ^                        ±            δ                          )            ⁢              xe2x80x83            ⁢              ⅇ                  j          ⁢                      xe2x80x83                    ⁢          θ          ⁢                      xe2x80x83                    ⁢                      (            t            )                                +                  n        ±            ⁢              xe2x80x83            ⁢              (        t        )            ⁢              xe2x80x83            ⁢      c      ⁢              xe2x80x83            ⁢                        (                      t            -                                          τ                ^                            ±              δ                                )                .            
Where t is time, xcfx84 is the relative timing error (fraction of a chip) between the transmitter and receiver, {circumflex over (xcfx84)} is the DLL estimate of the timing error, xcex4 is the correlator spacing which is restricted to a range of xcex4xe2x89xa6Tc, and Tc is the chip period. Typically xcex4 is set equal to             T      c        N    ,
where N is an integer larger than unity.
The subscript denotes the respective advanced or retarded signal. After integration and filtering, the energy is computed for each signal and then the two signals are subtracted to form a difference:                               e          ⁢                      xe2x80x83                    ⁢                      (            τ            )                          =                              "LeftBracketingBar"                                                                                2                    ⁢                    E                                                  ⁢                                  xe2x80x83                                ⁢                c                ⁢                                  xe2x80x83                                ⁢                                  (                                      t                    -                    τ                                    )                                ⁢                                  xe2x80x83                                ⁢                c                ⁢                                  xe2x80x83                                ⁢                                  (                                      t                    -                                          τ                      ^                                        -                    δ                                    )                                ⁢                                  xe2x80x83                                ⁢                                  ⅇ                                      j                    ⁢                                          xe2x80x83                                        ⁢                    θ                    ⁢                                          xe2x80x83                                        ⁢                                          (                      t                      )                                                                                  +                                                                    n                    -                                    ⁡                                      (                    t                    )                                                  ⁢                                  xe2x80x83                                ⁢                c                ⁢                                  xe2x80x83                                ⁢                                  (                                      t                    -                                          τ                      ^                                        -                    δ                                    )                                                      "RightBracketingBar"                    -                      "LeftBracketingBar"                                                                                2                    ⁢                    E                                                  ⁢                                  xe2x80x83                                ⁢                c                ⁢                                  xe2x80x83                                ⁢                                  (                                      t                    -                    τ                                    )                                ⁢                                  xe2x80x83                                ⁢                c                ⁢                                  xe2x80x83                                ⁢                                  (                                      t                    -                                          τ                      ^                                        +                    δ                                    )                                ⁢                                  xe2x80x83                                ⁢                                  ⅇ                                      j                    ⁢                                          xe2x80x83                                        ⁢                    θ                    ⁢                                          xe2x80x83                                        ⁢                                          (                      t                      )                                                                                  +                                                n                  +                                ⁢                                  xe2x80x83                                ⁢                                  (                  t                  )                                ⁢                                  xe2x80x83                                ⁢                c                ⁢                                  xe2x80x83                                ⁢                                  (                                      t                    -                                          τ                      ^                                        +                    δ                                    )                                                      "RightBracketingBar"                                              (        3        )            
The above expression ignores the filtering process for clarity. A loop filter having a bandwidth determined by the tracking dynamics and pull-in time requirements then filters this error signal. The output of the loop filter is sent to some further logic or becomes a stimulus signal depending on the sampling mechanism.
As is clear from expression (3), each of the DLL arm signals (arm signals are the signals present on an xe2x80x9carmxe2x80x9d of the DLL) has its phase components eliminated by a nonlinear squaring operation. The squaring results in a degradation of SNR. This degradation is a function of sampling bandwidth, loop bandwidth and input SNR. A large disadvantage of the squaring operation is that it causes increased degradation in loop SNR as the input SNR decreases. For narrow loop bandwidths the degradation in loop SNR is in the range of 3 to 8 dB, a clearly undesirable result.
In brief, some disadvantages of prior art methods of implementing DLLs for spread spectrum communications are that the DLL uses noncoherent tracking and it is very sensitive to fluctuations in signal magnitude due to the nonlinear squaring operation.
Prior art methods of implementing noncoherent time tracking loops have several disadvantages, such as high sensitivity to fluctuations in signal magnitude and increased degradation of signal to noise ratio SNR, due to the prior art""s reliance on nonlinear squaring operations to create an error signal for controlling signal sampling. Disclosed are innovative circuits and methods that eliminate the nonlinear squaring operation from the time tracking loop, thereby decreasing SNR degradation and improving fine synchronization capability to Direct Sequence Spread Spectrum signals. This improved ability to fine tune receiver synchronization to a DSSS signal is extremely useful in, for example, CDMA mobile telephones.
The disclosed innovations provide a coherent DLL scheme that has improved tracking performance. In the presently preferred embodiment, an innovative coherent DLL scheme is used with DSSS systems that have embedded pilot symbols or a pilot channel available. As an additional improvement, innovative methods and circuits to normalize the tracking loop error signal can be combined with the disclosed innovative DLL. Normalization of the error signal creates a DLL implementation robust to received signal amplitude variation.
The preferred embodiment advantageously eliminates the nonlinear squaring operations used to generate error signals by prior art time tracking loops. In the presently preferred embodiment, a CDMA receiver having a coherent Early-Late DLL uses the on-time signal to estimate the phase component of the Early and Late arms of the DLL. Because the estimated phase is known, the phase error term can be removed from the Early and the Late signals by multiplying by the complex conjugated on-time signal, instead of by the disadvantageous nonlinear squaring operation used in prior art techniques. After the phase terms are removed, the difference between the real components of the Early and Late signals is used as an error signal to finely control the A/D and Sample Generator of the CDMA receiver.
An alternative embodiment discloses further using the on-time signal to normalize the error signal before it is filtered, thus creating a DLL that is tolerant of received signal amplitude variation. The on-time signal is multiplied by its conjugate to yield an on-time signal composed of only real components (i.e., without phase terms). Normalization is accomplished by dividing the error signal by the real on-time signal. The resultant normalized error signal is used to control the A/D and Sample Generator.
Another alternative embodiment achieves an advantageous amplitude invariance by use of only the phase-removed Early and phase-removed Late signals to normalize the error signal before filtering. The on-time signal is not used for normalization. In a coherent DLL, the arm signals are multiplied by the conjugated on-time signal, which removes the phase terms from the arm signals, leaving only the real components of the arm signals. These real components are subtracted to yield an error signal that is normalized by division by the sum of the arm signals. A further advantage of this embodiment is that it is applicable to noncoherent, as well as coherent, time tracking loops. Noncoherent DLLs can implement this novel error signal normalization scheme by dividing the difference of the squared arm signals by the sum of the squared arm signals. Thus, noncoherent DLLs could use this inventive scheme to normalize the DLL error signal and achieve increased tolerance to received signal amplitude variation.